Description
The verilog output of https://github.com/ncihnegn/clash-with-stack/blob/master/src/PlayClash/Adder.hs
refAdder :: KnownNat n => Bit -> Vec n Bit -> Vec n Bit -> (Bit, Vec n Bit)
refAdder cin a b = (cout, res)
where cout :> res = bv2v $ (v2bv a `add` v2bv b) + boolToBV (bitToBool cin)
contains two redundant generate mappings:
// map begin
genvar i_0;
generate
for (i_0=0; i_0 < 32; i_0 = i_0 + 1) begin : map_0
wire map_in_0;
assign map_in_0 = b[i_0*1+:1];
wire [0:0] map_out_0;
assign map_out_0 = map_in_0;
assign c$scrut_app_arg_0[i_0*1+:1] = map_out_0;
end
endgenerate
// map end
// map begin
genvar i_1;
generate
for (i_1=0; i_1 < 32; i_1 = i_1 + 1) begin : map_1
wire map_in_1;
assign map_in_1 = a[i_1*1+:1];
wire [0:0] map_out_1;
assign map_out_1 = map_in_1;
assign c$scrut_app_arg_1[i_1*1+:1] = map_out_1;
end
endgenerate
// map end
I'd like to take this task if anyone can point me to the right direction.