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"Duplicate" names

Work started
Pull requests: 0
Contributors: 1
Level: Intermediate
  • Haskell
  • $25
Work started
Pull requests: 0
Contributors: 1
Level: Intermediate
  • Haskell
  • $25

On GitHub

Haskell to VHDL/Verilog/SystemVerilog compiler
More info >

Issue posted by: 
leonschoorl's avatar

Leon Schoorl

Description

When compiled to VHDL this example has a port named unsignedField1 and generates an internal signal named \unsignedField1\.
I'm not sure what the VHDL spec says about escaped names, but Quartus 18.1 thinks those are the same and throws an error.
Vivado seems fine with it though.

module NamingClashes where
import Clash.Prelude

data SomeType = SomeType { boolField :: Bool, unsignedField :: (Unsigned 3) } deriving (Generic,NFDataX)
i = SomeType False 3


topEntity clk rst = withClockResetEnable clk rst enableGen $ mealy @System f i

{-# ANN topEntity
  (Synthesize { t_name = "NamingClashes"
              , t_inputs = [ PortName "clk", PortName "rst"
                           , PortProduct "" [ PortName "", PortName "unsignedField1"]
                           ]
              , t_output = PortName "result"
              }
  )#-}

f s x = (new,out)
  where
    SomeType _ unsignedField  = x
    new = s{unsignedField = succ unsignedField}
    out = unsignedField > 3

Workaround: compile with -fclash-no-escaped-identifiers

  • Hacktoberfest
  • enhancement
  • external bug
  • intermediate

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On GitHub

Haskell to VHDL/Verilog/SystemVerilog compiler
More info >

Issue posted by: 
leonschoorl's avatar

Leon Schoorl

Use Open Source Issues to hire or get hired

"Duplicate" names
View on GitHub